Vlsi Projects

VLSI Projects
	Design and Implementation of a Field Programmable CRC Circuit Architecture---IEEE 2009.
	Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency---IEEE 2009.
	Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits---IEEE 2009.
	Design of Network-on-Chip Architectures with a Genetic Algorithm-Based Technique---IEEE 2009.
	Efficient On-Chip Crosstalk Avoidance CODEC Design---IEEE 2009.
	Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits---IEEE 2009.
	Fault Secure Encoder and Decoder for Memory Applications---IEEE 2007.
	A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture---IEEE 2009.
	A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System---IEEE 2008.
	A Generalization of a Fast RNS Conversion for a New 4-Modulus Base---IEEE 2009.
	A VLSI Progressive Coding for Wavelet-based Image Compression---IEEE 2007.
	A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter---IEEE 2009.
	A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations---IEEE 2009.
	FPGA Implementation of Viterbi Decoder---IEEE 200
	Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic---IEEE 2008.
	A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture---IEEE 2009.
	Designing Efficient Online Testable Reversible Adders with New Reversible Gate---IEEE 2007.
	Deviation-Based LFSR Reseeding for Test-Data Compression---IEEE 2009.
	Hardware implementation of Variable Precision Multiplication on FPGA---IEEE 2009.
	Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension---IEEE 2009.
	Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST---IEEE 2009.
	Spread Spectrum Image Watermarking with Digital Design---IEEE 2009.
	Superscalar Power Efficient Fast Fourier Transform FFT Architecture
	The Design and FPGA Implementation of GF (2128 ) Multiplier for Ghash---IEEE 2009.
	VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection---IEEE 2009.
	Left to Right Serial Multiplier for Large Numbers on FPGA.
	A Compact AES Encryption Core on Xilinx FPGA.
	A Novel Multiplexer based truncated array multiplier.

Admission Critiria process

Programme	For seats Through Counselling (By the Govt.)	Management quota seats
B.Tech	* Qualifying at EAMCET (Counselling Code : KTMC & KTMK)	** A pass in +2 in M.P.C. with atleast 60% either in aggregate or in group subjects or qualifying at EAMCET.
B.Ph	* Qualifying at EAMCET Either in Engg. Or Medical Stream (Counselling code : KIPH)	** A pass in +2 with M.P.C. or Bi.P.C. with 60% either in aggregate or in group subjects or qualifying in EAMCET Either in Engg. Or Medical Stream.
M.C.A.	* Qualifying at ICET (Counselling Code : KTMC & KOTM)	** A pass in any degree of a recognized University with Mathematics as one of the subjects and with atleast 60% either in aggregate or in group subjects or qualifying at ICET.
M.B.A.	* Qualifying at ICET (Counselling Code : KOTM & KTMC)	** A pass in any degree of a recognized University with atleast 60% either in aggregate or in group subjects or qualifying at ICET.
* Government of A.P. have been relaxing this clause as sufficient number of EAMCET qualified candidates were not available in the past few years. In such cases the candidates with qualifications as at ** Were admitted even in left over seats.

PROCESS OF ADMISSION Register your name with one of our following administrative offices along with a copy of intermediate marks memo for B.Tech. / B.Pharm and degree marks memo for MCA / MBA for admission against management quota seats soon after results of intermediate / degree examinations are a announced. (May & June). For counseling seats watch for news paper announcement by the State Council of Higher Education, Govt. of A.P.

OUR ADMINISTRATIVE OFFICES

Hyderabad Office 11-4-660, # 302, Ashok Chandra Enclave, Beside Ganga Jamuna Hotel, Lakdikapool, Hyderabad – 500 004. Telefax :040 – 23305639

Kurnool Office Ravi Prakash Complex, Opp : S.V. Complex, Near S.B.I. Main Branch, Kurnool. Ph : 08518 – 226822

Delhi Office Keshav Kabra, # 605, Hamilton Road, Zowarsingh Marg, Kashmiri Gate, Delhi – 110006. Ph : 09818202144

For Further Details, Contact : 98661 61111, 94901 97708, 94402 25699